1. Field of the Invention
This invention relates to a method and apparatus for effecting the logic simulation of a logic circuit system including a multi-port memory such as a multi-port RAM (random access memory).
2. Description of the Related Art
Broadly speaking, a multi-port RAM indicates a RAM having a plurality of independently addressable ports, each of the ports being write or read port, i.e., input or output port, respectively. Such a multi-port RAM has a function of permitting different addresses to be accessed via a plurality of ports, and it is possible to simultaneously access different addresses via a plurality of read ports so as to read out the stored contents in the respective addresses via the corresponding ports, for example.
Recently, this type of multi-port RAM can be manufactured at a low cost and is frequently used in an LSI (large scale integrated) circuit as a built-in RAM of the LSI circuit.
FIG. 1 shows an example of the conceptional construction of a multi-port RAM.
The multi-port RAM shown in FIG. 1 has a plurality of write ports WP1 to WPn and a plurality of read ports RP1 to RPm. The write ports WP1 to WPn are supplied with three types of inputs: write addresses WADDR1 to WADDRn, write data items WDATA1 to WDATAn and write enable signals WE1 to WEn. The read ports RP1 to RPm are supplied with readout addresses RADDR1 to RADDRm and output data readout outputs DOUT1 to DOUTm.
Generally, in a case where a logic circuit is constructed in the form of an LSI circuit, whether the logic circuit is correctly operated or not is evaluated and checked by use of a simulator. Therefore, when the LSI circuit is a logic circuit including a memory, it is necessary to simulate the write and read operations with respect to the memory by use of the simulator.
As the technique for effecting the simulation for the logic circuit including the memory, for example, the technique disclosed in U.S. Pat. No. 4,942,615 is known. In U.S. Pat. No. 4,942,615, the technique of evaluating a logic circuit having logic gates and memories by simulation is disclosed.
However, the conventional simulation technique including the technique disclosed in the above U.S. Patent is developed to deal with a logic circuit including only a RAM (different from a multi-port RAM) having one pair of write and read ports as a memory primitive. Therefore, with the conventional simulation technique, it is difficult to effectively effect the simulation of a logic circuit including a multi-port RAM which effects complicated operations.
Therefore, in general, when the simulation for the logic circuit including the multi-port RAM is effected, the RAM portion is separated from the main circuit portion, the logic circuit is divided into the input side logic circuit portion and the output side logic circuit portion, and they are separately simulated and evaluated.